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Layout Automation for Analog and Mixed-Signal Circuits Using Digital Place-and-Route Tools- [electronic resource]
Layout Automation for Analog and Mixed-Signal Circuits Using Digital Place-and-Route Tools- [electronic resource]
- 자료유형
- 학위논문
- Control Number
- 0016934422
- International Standard Book Number
- 9798380270755
- Dewey Decimal Classification Number
- 620
- Main Entry-Personal Name
- Wei, Po-Hsuan.
- Publication, Distribution, etc. (Imprint
- [S.l.] : Stanford University., 2021
- Publication, Distribution, etc. (Imprint
- Ann Arbor : ProQuest Dissertations & Theses, 2021
- Physical Description
- 1 online resource(108 p.)
- General Note
- Source: Dissertations Abstracts International, Volume: 85-03, Section: B.
- General Note
- Advisor: Horowitz, Mark;Lee, Thomas;Murmann, Boris.
- Dissertation Note
- Thesis (Ph.D.)--Stanford University, 2021.
- Restrictions on Access Note
- This item must not be sold to any third party vendors.
- Summary, Etc.
- 요약Today's analog and mixed-signal (AMS) layout flow requires long manual iterations and does not leverage computing resources for data-driven optimization. This issue is further compounded by the explosion of design rules and layout-dependent effects. We present an AMS layout generation flow that leverages digital place-and-route tools, amortizes setup cost with reusable primitives, and prunes layout candidates using time-efficient layout quality surrogates. We also analyze layoutdependent effects and parasitics and investigate unique challenges and mitigation strategies associated with using digital place-and-route tools for AMS circuits. These insights are validated with a generated 4x time-interleaved successive approximation analog-to-digital converter, a StrongARM comparator, and a voltage-controlled oscillator (VCO) in 16 nm FinFET CMOS. Silicon measurement results of the VCO closely track the simulation, showing only 6% in maximal oscillation frequency degradation from its manual counterpart, verifying the methodology from netlist to silicon.
- Subject Added Entry-Topical Term
- Circuits.
- Subject Added Entry-Topical Term
- Computer engineering.
- Subject Added Entry-Topical Term
- Layouts.
- Subject Added Entry-Topical Term
- Design.
- Subject Added Entry-Topical Term
- Transistors.
- Subject Added Entry-Topical Term
- Stem cells.
- Subject Added Entry-Topical Term
- Feedback.
- Subject Added Entry-Topical Term
- Engineers.
- Subject Added Entry-Topical Term
- Cellular biology.
- Subject Added Entry-Topical Term
- Electrical engineering.
- Added Entry-Corporate Name
- Stanford University.
- Host Item Entry
- Dissertations Abstracts International. 85-03B.
- Host Item Entry
- Dissertation Abstract International
- Electronic Location and Access
- 로그인을 한후 보실 수 있는 자료입니다.
- Control Number
- joongbu:643147