자료유형  

 학위논문

Control Number  

0017164884

International Standard Book Number  

9798346380863

Dewey Decimal Classification Number  

660

Main Entry-Personal Name  

Ko, Jung-Soo.

Publication, Distribution, etc. (Imprint  

[S.l.] : Stanford University., 2024

Publication, Distribution, etc. (Imprint  

Ann Arbor : ProQuest Dissertations & Theses, 2024

Physical Description  

109 p.

General Note  

Source: Dissertations Abstracts International, Volume: 86-05, Section: B.

General Note  

Advisor: Saraswat, Krishna.

Dissertation Note  

Thesis (Ph.D.)--Stanford University, 2024.

Summary, Etc.  

요약Silicon technology scaling is reaching its physical limits, which is triggering the need for alternative materials. Two-dimensional transition metal dichalcogenides (2D TMDs) are promising semiconductors showing good carrier mobility even at sub-nm channel thickness in metal oxide semiconductor (MOS) transistors. However, due to the lack of partially filled dangling bonds, atomic layer deposition (ALD) for ultrathin and highquality gate stacks on top of TMDs does not work well. As a result, fulfilling the technology requirement of sub-1 nm equivalent oxide thickness (EOT) on 2D TMDs has been challenging using industry-compatible materials and processes. In this work, I introduce three approaches to deposit ultrathin top gate dielectrics on 2D TMDs using CMOScompatible materials and processes that achieve 1-nm-scale top gate EOT.First, I investigate depositing ultrathin electron-beam evaporated seed layers that enable nucleation of high-κ dielectric ALD on monolayer MoS2 and WSe2. Several evaporated seed layer candidates (Si, Ge, Hf, Gd, La, Al2O3) are tested, and evaporated Si seed is revealed to work best for monolayer MoS2 transistors without damage and with good interfacial quality. Using Si seed layer followed by ALD of HfO2, top-gated monolayer TMD transistors are demonstrated which achieve top gate EOT of ~0.9 nm and minimum subthreshold swing of 70 mV/dec (at room temperature) with almost no hysteresis observed. This work also uncovers threshold voltage engineering by controlling the seed layer thicknesses.Next, I introduce nanofog aluminum oxide (AlOx) on monolayer MoS2 as the interfacial gate dielectric layer. Coverage of nanofog AlOx on monolayer MoS2 as a function of deposition temperature is studied, which reveals that deposition temperature of 50 °C provides most uniform coverage. Nanofog AlOx is also found to provide a high-quality dielectric interfacial layer on MoS2 compared to other seed layer deposition techniques. MoS2 transistors using nanofog AlOx followed by ALD HfO2 as top gate dielectric show negligible hysteresis and sufficiently good interface trap density that enable subthreshold swing of sub-100 mV/dec at room temperature. By using a bilayer gate dielectric stack of nanofog AlOx and HfO2, MoS2 transistors with 1-nm-scale top gate EOT are demonstrated with low gate leakage and excellent uniformity owing to the nanofog AlOx.

Subject Added Entry-Topical Term  

Aluminum.

Subject Added Entry-Topical Term  

Transmission electron microscopy.

Subject Added Entry-Topical Term  

Electrons.

Subject Added Entry-Topical Term  

Spectrum analysis.

Subject Added Entry-Topical Term  

Graphene.

Subject Added Entry-Topical Term  

Transistors.

Subject Added Entry-Topical Term  

Lasers.

Subject Added Entry-Topical Term  

Grain boundaries.

Subject Added Entry-Topical Term  

Molybdenum.

Subject Added Entry-Topical Term  

Analytical chemistry.

Subject Added Entry-Topical Term  

Atomic physics.

Subject Added Entry-Topical Term  

Optics.

Added Entry-Corporate Name  

Stanford University.

Host Item Entry  

Dissertations Abstracts International. 86-05B.

Electronic Location and Access  

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Control Number  

joongbu:655950