Material Type  

 학위논문

 

0017165064

Date and Time of Latest Transaction  

20250211153119

ISBN  

9798346786429

DDC  

620

Author  

Upton, Luke Robert.

Title/Author  

Peripheral Circuit Design Techniques for Emerging Memory.

Publish Info  

[S.l.] : Stanford University., 2024

Publish Info  

Ann Arbor : ProQuest Dissertations & Theses, 2024

Material Info  

208 p.

General Note  

Source: Dissertations Abstracts International, Volume: 86-06, Section: A.

General Note  

Advisor: Wong, H. S. Philip.

학위논문주기  

Thesis (Ph.D.)--Stanford University, 2024.

Abstracts/Etc  

요약As the capabilities of consumer electronics grow, so too does the need for low-energy, low-cost, and process-compatible embedded non-volatile memory (NVM). Resistive RAM (RRAM) is a technology that can meet this NVM need using materials and processes already available in a wide range of CMOS processes. However, (1) the read/write circuits required to access the information stored in a cell are often larger than the RRAM cells themselves in a macro, (2) there are competing pressures of decreasing read latency and increasing average read energy in an RRAM macro, and (3) the information stored in an RRAM cell must be retained even as the cell conductance experiences time-based variation. In this dissertation, we explore design methods for high-density, low energy RRAM storage macros. First, we present modeling approaches for RRAM macro readout circuit latency, energy, and thermal noise - spanning both voltage-based and current-based conductance sense amplifiers. From these models, we investigate the tradeoff between average read energy and input-referred thermal noise and find that there is not an inherent advantage in the voltage-based or current-based sensing scheme across all macro use cases. We then present a method to design small driver and pass gate circuits while providing the current and voltage necessary for RRAM cell write. The readout circuit models and write circuit area models are combined to generate prospective energy-area tradeoff curves for macro designs given RRAM cell parameters. This method allows designers to estimate read energy and macro density limits given an RRAM technology. Next, we demonstrate the Efficient Multiple-Bits-per-Cell Embedded RRAM (EMBER) macro, which uses the aforementioned read and write circuit design models/techniques to achieve a low read energy (1.0 pJ/bit single-bit-per-cell) with small unit cell area (5.6e-3 F2 single-bit-per-cell, F = 40 nm) compared to prior art. We also use experimental data obtained from EMBER to determine conductance level allocations most suitable for fast, low-BER write as well as conductance level allocations most suitable for low-energy, low-BER read over an extended period of time. Finally, we demonstrate that our read/write circuit design approach is not just applicable to RRAM, but to other emerging resistive NVMs as well.

Subject Added Entry-Topical Term  

Random access memory.

Subject Added Entry-Topical Term  

Space exploration.

Subject Added Entry-Topical Term  

Energy.

Subject Added Entry-Topical Term  

Macros.

Subject Added Entry-Topical Term  

Transistors.

Subject Added Entry-Topical Term  

Design techniques.

Subject Added Entry-Topical Term  

Aerospace engineering.

Subject Added Entry-Topical Term  

Computer science.

Subject Added Entry-Topical Term  

Design.

Added Entry-Corporate Name  

Stanford University.

Host Item Entry  

Dissertations Abstracts International. 86-06A.

Electronic Location and Access  

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Control Number  

joongbu:655283